1. Field of the Invention
This invention relates generally to integrated circuits (ICs) requiring for their correct operation a resistance element with a value predictable to within a few percent regardless of variations in the manufacturing process, changes in the IC operating temperature, or fluctuations in the voltage of the power supply energizing the IC. More particularly, the invention relates to delay cell circuits dependent upon an RC time constant predictable to within .+-.10% and in which a premium is placed on minimizing feedback circuitry and off-chip components used to stabilize the delay time. More particularly yet, the invention relates to the use of such RC time constants in ECL delay cells used in delay lines and ring oscillators.
2. Prior Art
One of the tradeoffs for the benefits provided by high-density IC chip technology is that the variance from one chip to another in the behavior of nominally-identical circuit elements is huge when compared with what prevailed in the old discrete-element days. Furthermore, the forms of these elements which have been adapted to integrated production often have greater dependence on circuit operating temperature and power supply voltage levels than was the case with the discrete elements. The variance in the as-fabricated product arises from the nature of the integrated fabrication sequence and the fact that the various heat treatments needed to achieve a particular end configuration on a chip all are interrelated in their effects on the IC components contained within the chip.
Of the components displaying fabrication-related variations, resistors are perhaps the worst, with as-fabricated resistance tolerances being .+-.25% or more with respect to the nominal design resistance. Further, IC resistors will in general vary significantly in resistance during circuit operation in response to temperature changes. Fortunately, most circuits do not depend upon the absolute value of any particular resistance. They depend, rather, on ratios of resistances. Because of this, most variations in resistance values-whether due to fabrication vagaries, operating temperatures drift, or power-supply-voltage fluctuations-cancel out. One important category of exceptions to this situation is the delay cell circuit, widely used to produce propagation delays, usually in ring oscillator circuits. These propagation delays depend ultimately on RC time constants and consequently on the absolute value of a resistance. (They actually depend on the absolute value of the product of resistance and capacitance. To the extent that the capacitive element is affected by transistor junction capacitance, that element can also vary a great deal due to process, temperature, and voltage fluctuations.)
The present invention is directed toward producing an effective IC resistive element having a much lower dependence on the fabrication process and also a much lower dependence on operating temperature. Relatively speaking, it is a process-independent, temperature-independent resistance. More accurately described, it constitutes apparatus and method for producing a resistance which is compensated to first order for process and temperature fluctuations by a technique which itself is V.sub.cc -independent. Because the greatest utility for such a resistance appears to lie with delay cells, the preferred embodiment of the present invention lies with delay cells. In this preferred embodiment, the compensated resistance of the present invention is coupled with a stable, low-tolerance capacitance so as to produce an RC element compensated for process, temperature, and voltage. Since the most common application of delay cells is to ring oscillators, the prior art most relevant to the present invention is that dealing with ring oscillators.
Because of the variance in as-fabricated RC values and also the variation of RC values with temperature and V.sub.cc (the power supply voltage), ring oscillators tend to produce uncorrected output frequencies which deviate significantly from the design frequency. Since ring oscillators are normally configured so that they are voltage-"tunable" (i.e., as voltage-controlled-ring-oscillators-VCROs), provision can be made for a feedback mechanism to lock the VCRO output frequency at any value within the capture range of the underlying circuit. The feedback mechanism generates an error voltage V.sub.error proportional to the phase-deviation between the VCRO output and some reference frequency; a VCRO stabilized in such a manner is a Phase-Locked Loop (PLL). This implies a ring oscillator input coupled to an element which provides a shift in the frequency in response to the voltage signal, V.sub.error. Since the range in magnitude of the error signal is not large, the sensitivity of the frequency response to V.sub.error --.increment.f/.increment.V.sub.error --must be high, and the greater the potential frequency deviation from design, the higher .increment.f/.increment.V.sub.error must be. [Since the ring oscillator's operation depends on a series (cascade) of delay cells, the shift which is actually being effected is in delay time, T. Thus, the sensitivity can also be expressed by the size of .increment.T/.increment.V.sub.error.] The disadvantage of a VCRO highly responsive to V.sub.error is that its frequency is also highly responsive to electrical noise and to power-supply-bounce-induced voltage changes in the circuit-which are passed through as phase jitter on the VCRO output.
Until a few years ago, IC delay cells predominantly used TTL circuitry, with the T-sensitive parameter being the supply voltage V.sub.cc. For reasons which became increasingly important--including faster switching speeds, lower signal swings (and hence lower EMI problems), lower power dissipation--ECL-based delay cells offered advantages over the TTL circuitry. For many applications the ECL delay cell disclosed in U.S. Pat. No 4,876,519 (1989), issued to Davis et al. ("High Frequency ECL Voltage Controlled Ring Oscillator") has now become the standard. The ECL delay cell of Davis et al. depends for its V.sub.error -sensitive element on the actual resistors--the load resistors-- establishing the delay cell's RC time constant. More particularly, the Davis et al. device provides for the load resistors to be P-channel resistors coupled between V.sub.cc and the collectors of the emitter-coupled input transistors. The error voltage V.sub.error is then applied (though indirectly) to the gates of these load resistors in order to exercise the necessary T-control.
In spite of the advantages of the ECL delay cell of Davis et al., it shares with the TTL family of delay cells the wide as-fabricated frequency variance referred to above. Because the uncorrected frequency of the resultant ring oscillators may vary from the nominal design value by .+-.35% or more, the circuitry must have high sensitivity to V.sub.error. Compounding the annoyance of the resulting jitter, the need for closed-loop control for the oscillator leads to a more complicated circuit on the chip and hence to an increase in the chip price beyond what it would otherwise be. Furthermore, it is not possible with present technology to put all of the feedback circuitry on the chip, leading to the frequent necessity of subsequently adding off-chip circuit components to the IC chip when the latter is incorporated into an extended circuit. This requirement further drives up the ultimate cost of production.
Ironically, many delay line and ring oscillator applications do not require the high precision of a PLL or its equivalent. Although the .+-.35% (or greater) variance in all of the relevant prior art is unacceptably large, a delay cell which could provide an uncorrected T predictable to within .+-.10% would satisfy the needs of many applications with no further correction, which means that the PLL--and all of the disadvantages it presents--represents overkill in those situations. Furthermore, for those applications requiring higher precision, a cell with an as-fabricated variance of .+-.10% will, when incorporated into a PLL, satisfy those applications with much less jitter than the present circuits. (I.e., with the narrow variance to be corrected, these cells would not require the high .increment.T/.increment.V.sub.error sensitivity of traditional, broad tolerance, cells.)
Therefore, what is needed is a circuit with an RC element presenting an as-fabricated predictability to within less than .+-.10% over the circuit's operating temperature range and power supply voltage fluctuation range. What is further needed is that this predictability be attained without complicated feedback circuitry--such as is present in a PLL--without any resistor-"trimming," and with a minimum dependence on off-chip components.